The present invention relates to a data interface for a memory array. More specifically, the present invention relates to transformation logic to enable data to be efficiently written to and then read from a memory array.
Non-volatile memory arrays are typically operated as follows. Initially, all of the memory cells of the array are erased. In the case of a non-volatile memory array, this means that all of the non-volatile memory cells in the array have a low threshold voltage, or a logic xe2x80x9c1xe2x80x9d value. In order to store a logic xe2x80x9c0xe2x80x9d value in a memory cell, the memory cell must be programmed. Programming is typically performed by hot electron injection or Fowler-Nordheim tunneling. Unfortunately, programming a single non-volatile memory cell requires a significant amount of power, and stresses the memory cell. Programming more than one non-volatile memory cell requires an even larger amount of power. For a low power device, there may be a limit to the number of memory cells that can be programmed at the same time. For example, in some low power devices, only eight memory cells may be programmed at a time.
It would therefore be desirable to have a method and apparatus for decreasing the number of non-volatile memory cells that must be programmed, thereby saving power and reducing the stress applied to the memory cells.
Accordingly, the present invention provides a method and apparatus for reducing the number of memory cells that must be programmed in a memory array. More specifically, the present invention uses data translation to reduce the number of memory cells that must be programmed in a memory array.
In one embodiment, a memory system includes a logic comparator coupled to receive a write data word to be stored in a memory array. The logic comparator determines whether more than half of the bits of the write data word require a program operation. In response, the logic comparator provides a status signal having a first state if more than half of the bits of the write data word must be programmed, and having a second state if half or fewer of the bits of the write data word must be programmed. The status signal is provided to an input translation circuit, which passes the write data word to the memory array as an input data word if the status signal has the second state, and passes the inverse of the write data word to the memory array as an input data word if the status signal has the first state. Then both the input data word and the corresponding status signal are written to the memory array. In one embodiment, the first state of the status signal is selected to correspond with the programmed state of a memory cell in the memory array.
An output translation block is coupled to receive a data word and the corresponding status signal read from the memory array. If the status signal read from the memory array has the second state, then the output translation block passes the data word read from the memory array without modification. If the status signal read from the memory array has the first state, then the output translation block passes the inverse of the data word read from the memory array.
In this manner, the memory system provides the proper read data values, while minimizing the number of memory cells in the memory array that must be programmed. The maximum number of memory cells that must be programmed during any write operation is reduced by half in accordance with the present invention.
The present invention will be more fully understood in view of the following description and drawings.